A Clock and Data Recovery (CDR) circuit is used in high-speed serial data systems where a clock is not run separately from the data (known as forwarded clock) but rather is embedded in the serial data stream, which is just series of random binary ones and zeros. The clock is then extracted from the data stream via a CDR circuit. The data is sampled or sliced, and retimed. This portion is the known at the data recovery in a CDR.

A CDR circuit is implemented in the receiver where the data stream or signals are amplified, filtered and equalized.  A slicer circuit will then chop the data stream into sections using a precisely generated frequency. A Phased Lock Loop (PLL) is used to lock on to the frequency of the embedded clock of the data stream. This embedded clock will be the reference clock to the PLL.  The PLL is used to regenerate a clock that is locked in phase to the reference clock. The two phases of the reference clock and the newly generated clock are aligned by the PLL.  The recovered clock is then used to regenerate the received data.

PLLs are a commonly used in CDR circuits, however, other types of oscillators have also been used in CDR circuits. The choice often depends on the tradeoffs for each design and performance requirements of the CDR.

The result of the CDR is a clock and data now separated from each other and can be used in other sections of digital circuitry and logic as desired.